Hybrid silicon laser have been developed that can produce terabit-level optical computer data pipes for high-performance computing applications. Using standard silicon manufacturing processes, the light-emitting properties of Indium Phosphide (InP) may be combined with the light-routing capabilities of silicon into a single hybrid chip. When voltage is applied, light generated in the InP enters the silicon waveguide to create a continuous laser beam that can be used to drive other silicon photonic devices.
Generally, silicon-on-insulator (SOI) devices produce heat when operating which should be managed. FIG. 1 shows a simple diagram of a typical SIO wafer. Silicon-on-insulator wafers may include a basic three layer structure. The top silicon epitaxial layer acts as a waveguide 100, with the SiO2 buried oxide layer 102 acting as a lower cladding confining the optical mode and stopping it leaking into the lower silicon substrate 104. Typical thicknesses for this buried oxide layer 102 is 0.35 μm for waveguides taller than 2.5 μm and 1 μm for waveguides shorter than 1.5 μm in height.
For optical devices that generate heat when they operate, e.g. hybrid lasers or amplifiers, the thermal resistance between the heat source and heat sink is a key device parameter as it dictates the actual working temperature of the active area of the device. Typically for devices built on SOI the heat sink is placed underneath the silicon substrate 104 and typically is a thermoelectric cooler (TEC) device (not shown). For small waveguides (<1.5 μm) that use this thermal architecture, the SiO2 buried oxide layer is the dominant source of thermal resistance (compare the thermal conductivity of SiO2 (1.1-1.4 W/m.K) to that of Silicon (130 W/m.K)).
FIG. 2A shows a typical cross-section of a hybrid laser structure. As above, it may include an SOI structure comprising a silicon epitaxial layer that as a waveguide 200, with the SiO2 buried oxide layer 202 acting as a lower cladding confining the optical mode and stopping it leaking into the lower silicon substrate 204. The laser may comprise a InP p-cladding 208, an active region 210, an InP—H+ implant region 212 over a InGaAsP n-contact layer 214 and an Au contact 216.
FIG. 2B shows a simulation of the temperature profile in this same device when 1.5 W of electrical power is dissipated. Current in the device flows from the p-contact, through the p-InP cladding layer 208 to the active region 210, then through the n-contact layer 210 to the n-metal. As can be seen in FIG. 2B significant device heating occurs in the active region of the laser. This leads to degraded device performance, such as reduced output power and increased threshold currents. The thermal impedance of this device is about 44.3 0C/W